Calibration of multiple parallel data communications lines for high skew conditions
US8681839B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 27, 2010 |
| Grant date | Mar 25, 2014 |
| Priority date | — |
| Expiry date | Sep 21, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0337
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A parallel data link includes a redundant line. A bank of switches permits any arbitrary line of the link to be enabled or disabled for carrying functional data, each line being dynamically calibrated in turn by disabling the line and allowing other lines to carry the functional data. The switches are located downstream of alignment mechanisms so that data input to the switches is compensated for data skew. Preferably, receiver synchronization circuitry in each line operates in a respective independent clock domain, while the switches and calibration mechanism operate in a common clock domain. Preferably, the receiver synchronization circuits provide an adjustable delay corresponding to a variable number of clock cycles to align the outputs of the receiver synchronization circuits with respect to one another, which can accommodate high data skew.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.