Inventor · Round Rock, TX, US

Michael B. Spear

17Patents
6h-index
33Co-inventors
62Inventor score

Filing activity: Feb 11, 2005 → Nov 28, 2022

Most-cited inventions

PatentTitleAreaCited byStatus
US8898504B2 Parallel data communications mechanism having reduced power continuously calibrated lines Electricity 58 Active
US8139430B2 Power-on initialization and test for a cascade interconnect memory system Emerging Cross-Sectional Technologies 39 Active
US8681839B2 Calibration of multiple parallel data communications lines for high skew conditions Electricity 13 Active
US9474034B1 Power reduction in a parallel data communications interface using clock resynchronization Emerging Cross-Sectional Technologies 10 Active
US8767531B2 Dynamic fault detection and repair in a data communications mechanism Electricity 9 Active
US7412618B2 Combined alignment scrambler function for elastic interface Electricity 7 Active
US10698440B2 Reducing latency of memory read operations returning data on a read data path across multiple clock boundaries, to a host implementing a high speed serial interface Physics 5 Active
US9092312B2 System and method to inject a bit error on a bus lane Physics 3 Active
US8001412B2 Combined alignment scrambler function for elastic interface Electricity 2 Active
US11099601B2 Reducing latency of memory read operations returning data on a read data path across multiple clock boundaries, to a host implementing a high speed serial interface Physics 1 Active
US10608763B2 Built-in self-test for receiver channel Electricity 1 Active
US9715270B2 Power reduction in a parallel data communications interface using clock resynchronization Emerging Cross-Sectional Technologies 1 Active
US10771068B2 Reducing chip latency at a clock boundary by reference clock phase adjustment Physics 0 Active
US10162773B1 Double data rate (DDR) memory read latency reduction Physics 0 Active
US11973630B1 Calibrating a quadrature receive serial interface Electricity 0 Active
US11907074B2 Low-latency deserializer having fine granularity and defective-lane compensation Physics 0 Active
US10901936B2 Staged power on/off sequence at the I/O phy level in an interchip interface Physics 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.