Method for optimizing memory controller placement in multi-core processors using a fitness metric for a bit vector of EAH memory controller
US8682815B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 20, 2013 |
| Grant date | Mar 25, 2014 |
| Priority date | — |
| Expiry date | Mar 20, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/394
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The location of the memory controllers within the on-chip fabric of multiprocessor architectures plays a central role in latency bandwidth characteristics of the processor-to-memory traffic. Intelligent placement substantially reduces the maximum channel load depending on the specific memory controller configuration selected. A variety of simulation techniques are used along and in combination to determine optimal memory controller arrangements. Diamond-type and diagonal X-type memory controller configurations that spread network traffic across all rows and columns in a multiprocessor array substantially improve over other arrangements. Such placements reduce interconnect latency by an average of 10% for real workloads, and the small number of memory controllers relative to the number of on-chip cores opens up a rich design space to optimize latency and bandwidth characteristics of the on-chip network.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.