Memory controller with suspend feature
US8683166B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 25, 2010 |
| Grant date | Mar 25, 2014 |
| Priority date | — |
| Expiry date | Dec 21, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1774
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A programmable integrated circuit device (IC) can include a configuration controller configured to assert a suspend request signal responsive to an input triggering suspend mode within the programmable IC and a memory controller block coupled to the configuration controller and a memory device. The memory controller block can be configured to place the memory device in self refresh mode in response to the suspend request signal and assert a suspend acknowledgement signal subsequent to placing the memory device in self refresh mode. The configuration controller can continue implementing suspend mode within the programmable IC in response to assertion of the suspend acknowledgement signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.