Integrated circuit optimization
US8683416B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 28, 2011 |
| Grant date | Mar 25, 2014 |
| Priority date | — |
| Expiry date | May 13, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/396
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A device may identify signal channels for connecting circuit blocks, where each circuit block is associated with a block implementation area corresponding to a substrate. The device may assign a channel priority to each of the signal channels based on at least one channel criteria. The device may allocate a channel implementation area, corresponding to the substrate, for each of a plurality of signal channels, based on the channel priority assigned to the signal channel and based on the block implementation areas. The device may generate an integrated circuit design comprising the channel implementation area allocated for each of the plurality of signal channels.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.