Methods for forming through vias
US8685798B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 14, 2013 |
| Grant date | Apr 1, 2014 |
| Priority date | — |
| Expiry date | Jun 14, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods for forming through vias in an integrated circuit package are disclosed. A substrate having a first surface is covered with an encapsulation layer of uncured material; the method includes inserting an upper mold tool having a first plurality of pillars into the encapsulation layer to imprint through vias extending to the first surface of the substrate; curing the encapsulation layer and the through vias; removing the upper mold tool from the encapsulation layer; and disposing conductor material within the through vias to make electrical connectors within the through vias. In additional methods, a method for forming an encapsulation layer using an upper and lower mold tool to form through vias and a mold cavity is disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.