Method of forming a shallow trench isolation embedded polysilicon resistor
US8685818B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 25, 2010 |
| Grant date | Apr 1, 2014 |
| Priority date | — |
| Expiry date | May 1, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/811
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Forming a polysilicon embedded resistor within the shallow trench isolations separating the active area of two adjacent devices, minimizing the electrical interaction between two devices and reducing the capacitive coupling or leakage therebetween. The precision polysilicon resistor is formed independently from the formation of gate electrodes by creating a recess region within the STI region when the polysilicon resistor is embedded within the STI recess region. The polysilicon resistor is decoupled from the gate electrode, making it immune to gate electrode related processes. The method forms the polysilicon resistor following the formation of STIs but before the formation of the p-well and n-well implants. In another embodiment the resistor is formed following the formation of the STIs but after the formation of the well implants.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.