Vertical channel memory devices with nonuniform gate electrodes and methods of fabricating the same
US8685821B2 · kind B2 · utility
5Cited by
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15Claims
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Key dates
| Filing date | Sep 6, 2013 |
| Grant date | Apr 1, 2014 |
| Priority date | — |
| Expiry date | Sep 6, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/694
Abstract
A mold stack including alternating insulation layers and sacrificial layers is formed on a substrate. Vertical channel regions extending through the insulation layers and sacrificial layers of the mold stack are formed. Gate electrodes are formed between adjacent ones of the insulation layers and surrounding the vertical channel regions. The gate electrodes have a greater thickness at a first location near sidewalls of the insulation layers than at a second location further away from the sidewalls of the insulation layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.