3D chip package with shielded structures
US8686543B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 28, 2011 |
| Grant date | Apr 1, 2014 |
| Priority date | — |
| Expiry date | Jan 3, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/157
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A 3D chip package is disclosed that includes a carrier substrate with a first cavity and a second cavity formed therein. A first structure is attached to the carrier substrate at least partially in the first cavity, and a second structure is attached to the carrier substrate at least partially in the second cavity, where the first and second structures include electrical circuitry. A shield layer may be disposed between the carrier substrate and the first structure and/or the second structure for isolating the first structure and/or the second structure at least one of electrically, magnetically, optically, or thermally. In some embodiments, the shield layer may be a dielectric shield layer for dielectrically coupling the first structure and the second structure. The first structure and the second structure may be homogeneous or heterogeneous.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.