Stack die structure for stress reduction and facilitation of electromagnetic shielding
US8686547B1 · kind B1 · utility
5Cited by
0References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 22, 2011 |
| Grant date | Apr 1, 2014 |
| Priority date | — |
| Expiry date | Sep 10, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/351
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present disclosure describe a packaged semiconductor device that reduces stress on a semiconductor device caused by thermal expansion of the insulating material used in the packaged semiconductor device. In one embodiment, an inactive semiconductor device is coupled to the top of active semiconductor device. Both the inactive and active devices are encapsulated by the insulating material. The configuration of the inactive device is selected based on its ability to absorb the expansion of the insulating material at operating temperature.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.