Multi-bit resistive-switching memory cell and array
US8687432B2 · kind B2 · utility
6Cited by
6References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 17, 2012 |
| Grant date | Apr 1, 2014 |
| Priority date | — |
| Expiry date | Oct 25, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/53
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
This invention proposes a multi-bit resistive-switching memory cell and array thereof. Multiple conduction paths are formed on each memory cell and independent of each other, and each conduction path can be in a high-resistance or low-resistance state, so as to form a multi-bit resistive-switching memory cell. A memory cell array can be formed by arranging a plurality of multi-bit resistive-switching memory cells, and the memory cell array provides a simple, high density, high performance and cost-efficient proposal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.