Method and apparatus for receiver adaptive phase clocked low power serial link
US8687752B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 1, 2011 |
| Grant date | Apr 1, 2014 |
| Priority date | — |
| Expiry date | Mar 9, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/091
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A serial bit stream having a given bit per second rate is received and distributed to a plurality of phase shifted samplers. A multi-phase sampling trigger is generated at a rate lower than the given bit per second rate, and each of the phase shifted samplers is controlled by one of the phases of the multi-phase sampling trigger. The time spacing between phases of the multi-phase sampling trigger is the inverse of the given bit per second rate. The phase of the multi-phase sampling trigger is aligned with the phase of the serial bit, to collectively recover by the plurality of phase shifted samplers a plurality of consecutive bits from the serial bit stream.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.