Hardware acceleration apparatus, method and computer-readable medium efficiently processing multi-core synchronization
US8688885B2 · kind B2 · utility
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14Claims
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Key dates
| Filing date | Oct 14, 2010 |
| Grant date | Apr 1, 2014 |
| Priority date | — |
| Expiry date | Nov 22, 2031 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Provided is a hardware acceleration apparatus, method and computer-readable medium efficiently processing multi-core synchronization. A processor core that fails to acquire a lock variable may be switched to a low power sleep mode and a waste of power may be reduced. Additionally, when a lock variable is returned, a wakeup signal may be transmitted to a processor core operated in the low power sleep mode, and the processor core may be activated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.