Transparent processing core and L2 cache connection
US8688911B1 · kind B1 · utility
0Cited by
15References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Nov 23, 2009 |
| Grant date | Apr 1, 2014 |
| Priority date | — |
| Expiry date | Jan 28, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0811
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present disclosure provide a system on a chip (SOC) comprising a processing core including a core bus agent, a bus interface unit (BIU), and a bridge module operatively coupling the processing core to the BIU, the bridge module configured to selectively route information from the core bus agent to a cache or to the BIU by bypassing the cache. Other embodiments are also described and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.