Memory sharing between embedded controller and central processing unit chipset
US8688944B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 20, 2011 |
| Grant date | Apr 1, 2014 |
| Priority date | — |
| Expiry date | Apr 23, 2032 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An embedded controller includes a microcontroller core and memory control circuitry. The memory control circuitry is configured to communicate with a Central Processing Unit (CPU) chipset over a first Serial Peripheral Interface (SPI), for which bus arbitration is not supported, at a first clock rate, to communicate with a memory over a second SPI at a second, fixed clock rate, to relay memory transactions between the CPU chipset and the memory over the first and second SPIs, to identify time intervals in which no memory transactions are relayed on the second SPI and to retrieve from the memory information for operating the microcontroller core during the identified time intervals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.