Programmable exception processing latency
US8688964B2 · kind B2 · utility
1Cited by
3References
22Claims
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Key dates
| Filing date | May 10, 2010 |
| Grant date | Apr 1, 2014 |
| Priority date | — |
| Expiry date | Nov 17, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A digital processor with programmable exception processing latency, may have a central processing unit (CPU) of a digital processor, an exception controller coupled with the CPU, and a control register coupled with the CPU, wherein the control register is operable to set the operation mode of the CPU in at least one of two modes, wherein in the first mode the CPU has a fixed exception processing latency time, and in a second mode the CPU has a variable exception processing latency time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.