Patent · US Active

Scheduling of instructions

US8689202B1 · kind B1 · utility

20Cited by
49References
15Claims
0Family size

Assignee

Inventors

Key dates

Filing dateMar 30, 2005
Grant dateApr 1, 2014
Priority date
Expiry dateOct 13, 2028

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG06F8/445
  • WIPO fieldComputer technology
  • WIPO sectorElectrical engineering

Abstract

A method of automatically extracting information from an architecture description. A memory resident directed acyclic graph data structure comprising nodes representing instructions and edges whose weights represent dependencies between pairs of instructions is constructed. A list of ready nodes are maintained in the directed acyclic graph. A list of nodes not scheduled is maintained. And, it is determined whether the next instruction to be scheduled is to be taken from the list of ready nodes or from the list of nodes not yet scheduled.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.