Tamper detector for secure module
US8689357B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 19, 2012 |
| Grant date | Apr 1, 2014 |
| Priority date | — |
| Expiry date | Dec 11, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F21/755
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A tamper detector has input and output pins for connection to ends of a tamper detection circuit, and a corresponding set of linear feedback shift registers (LFSRs) timed by clock signals for generating pseudo-random coded detection signals as a function of seed values and of a generator polynomial defined by feedback taps. A comparator compares signals received from the detection circuit with the coded detection signals. A multiplexer provides the coded detection signal selectively from the LFSRs to the output pin and the comparator. A controller varies the seed values for different cycles of values of the pseudo-random coded detection signals. The controller also controls the generator polynomial and a frequency of the clock signals for different cycles of values of the pseudo-random coded detection signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.