Passive devices for FinFET integrated circuit technologies
US8692291B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 27, 2012 |
| Grant date | Apr 8, 2014 |
| Priority date | — |
| Expiry date | Apr 14, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/713
Abstract
Device structures, design structures, and fabrication methods for passive devices that may be used as electrostatic discharge protection devices in fin-type field-effect transistor integrated circuit technologies. A device structure is formed that includes a well of a first conductivity type in a device region and a doped region of a second conductivity in the well. The device region is comprised of a portion of a device layer of a semiconductor-on-insulator substrate. The doped region and a first portion of the well define a junction. A second portion of the well is positioned between the doped region and an exterior sidewall of the device region. Another portion of the device layer may be patterned to form fins for fin-type field-effect transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.