Phase-locked loop frequency stepping
US8692594B2 · kind B2 · utility
2Cited by
2References
20Claims
0Family size
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Key dates
| Filing date | Dec 19, 2011 |
| Grant date | Apr 8, 2014 |
| Priority date | — |
| Expiry date | Jan 23, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/183
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method and a phase-locked loop (PLL) for generating output clock signals with desired frequencies are described. The PLL is equipped with a ramp generator that increments or decrements a feedback divider value before providing it to a modulator. The modulator modulates the feedback divider value and provides the modulated value to a feedback divider of the PLL for performing frequency division.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.