Over-limit electrical condition protection circuits for integrated circuits
US8693148B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 8, 2009 |
| Grant date | Apr 8, 2014 |
| Priority date | — |
| Expiry date | Jan 10, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/713
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
Integrated circuits, memories, protection circuits and methods for protecting against an over-limit electrical condition at a node of an integrated circuit. One such protection circuit includes a snapback circuit having at least a portion formed in an isolated doped well region and configured to switch to a low impedance state in response to an input exceeding a trigger condition and further having a control circuit electrically coupled to a reference voltage and further electrically coupled to the isolated doped well region and the portion of the snapback circuit formed in the doped well region. The control circuit includes an impedance adjustable in response to a control signal and configured to adjust an isolated doped well impedance in which at least a portion of the snapback circuit is formed relative to the reference voltage. A modulated trigger and hold condition for the snapback circuit can be set according to a control signal adjusting an electrical impedance of the control circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.