Signal synchronization in multi-voltage domains
US8693267B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 23, 2009 |
| Grant date | Apr 8, 2014 |
| Priority date | — |
| Expiry date | Sep 17, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/413
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and a method to improve signal synchronization in a plurality of signal paths traversing multiple voltage domains. According to an embodiment of the present disclosure a memory arrangement is preferred for signal synchronization. All read/write and clocks signals and other control signals are driven to periphery supply (Vp) levels, except wordline (WL[i]) signals which are driven at core supply (Vc) level. By doing so, lower average and peak current consumption associated with core supply (Vc) is achieved with constant delays and maintaining required signal synchronization in the signal paths traversing multiple voltage domains.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.