Memory device for managing timing parameters
US8693269B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 8, 2012 |
| Grant date | Apr 8, 2014 |
| Priority date | — |
| Expiry date | Sep 27, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2272
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of performing write operations in a memory device including a plurality of bank is performed. Each bank includes two or more sub-banks including at least a first sub-bank and a second sub-bank. The method comprises: performing a first row cycle for writing to a first word line of the first sub-bank, the first row cycle including a plurality of first sub-periods, each sub-period for performing a particular action; and performing a second row cycle for writing to a first word line of the second sub-bank, the second row cycle including a plurality of second sub-periods of the same type as the plurality of first sub-periods. The first row cycle overlaps with the second row cycle, and a first type sub-period of the first sub-periods overlaps with a second type sub-period of the second sub-periods, the first type and second type being different types.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.