Satisfying memory ordering requirements between partial reads and non-snoop accesses
US8694736B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 21, 2012 |
| Grant date | Apr 8, 2014 |
| Priority date | — |
| Expiry date | Aug 21, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/70
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for preserving memory ordering in a cache coherent link based interconnect in light of partial and non-coherent memory accesses is herein described. In one embodiment, partial memory accesses, such as a partial read, is implemented utilizing a Read Invalidate and/or Snoop Invalidate message. When a peer node receives a Snoop Invalidate message referencing data from a requesting node, the peer node is to invalidate a cache line associated with the data and is not to directly forward the data to the requesting node. In one embodiment, when the peer node holds the referenced cache line in a Modified coherency state, in response to receiving the Snoop Invalidate message, the peer node is to writeback the data to a home node associated with the data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.