Patent · US Active

Systems and methods for super-threading of integrated circuit design programs

US8694931B1 · kind B1 · utility

0Cited by

9References

9Claims

0Family size

Assignee

Cadence Design Systems, Inc. · US

Inventor

Denis Baylor · Cupertino, US

Key dates

Filing date	Feb 20, 2011
Grant date	Apr 8, 2014
Priority date	—
Expiry date	Feb 20, 2031

Classification

Technology area (CPC G)Physics
CPC primaryG06F30/327
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

In one embodiment of the invention, a method is disclosed including receiving a netlist of an integrated circuit design; executing a first copy of an integrated circuit design program with a first processor associated with a first memory space to independently perform work on a first portion of the integrated circuit design; and executing a second copy of the integrated circuit design program with a second processor associated with a second memory space to independently perform work on a second portion of the integrated circuit design; wherein the second memory space is independent of the first memory space.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.