Mixed operating performance modes including a shared cache mode
US8695011B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 27, 2012 |
| Grant date | Apr 8, 2014 |
| Priority date | — |
| Expiry date | Jun 13, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/5077
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Functionality is implemented to determine that a plurality of multi-core processing units of a system are configured in accordance with a plurality of operating performance modes. It is determined that a first of the plurality of operating performance modes satisfies a first performance criterion that corresponds to a first workload of a first logical partition of the system. Accordingly, the first logical partition is associated with a first set of the plurality of multi-core processing units that are configured in accordance with the first operating performance mode. It is determined that a second of the plurality of operating performance modes satisfies a second performance criterion that corresponds to a second workload of a second logical partition of the system. Accordingly, the second logical partition is associated with a second set of the plurality of multi-core processing units that are configured in accordance with the second operating performance mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.