Silicon wafer reclamation process
US8696930B2 · kind B2 · utility
0Cited by
9References
7Claims
0Family size
Assignee
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Key dates
| Filing date | Nov 23, 2010 |
| Grant date | Apr 15, 2014 |
| Priority date | — |
| Expiry date | Jul 21, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/31111
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An etchant for removing a porous low-k dielectric layer on a semiconductor substrate includes a hydrofluoric acid-based solvent, a dilating additive for dilating the pores in the porous low-k dielectric, and a passivating additive that forms a passivation layer at the interface between the low-k dielectric layer and the semiconductor substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.