Method of forming a semiconductor structure
US8697505B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 15, 2011 |
| Grant date | Apr 15, 2014 |
| Priority date | — |
| Expiry date | Oct 2, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/8503
Abstract
A semiconductor structure is disclosed. The semiconductor structure includes a first layer. A second layer is disposed on the first layer and different from the first layer in composition. An interface is between the first layer and the second layer. A third layer is disposed on the second layer. A gate is disposed on the third layer. A source feature and a drain feature are disposed on opposite sides of the gate. Each of the source feature and the drain feature includes a corresponding metal feature at least partially embedded in the second and the third layer. A corresponding intermetallic compound underlies each metal feature. Each intermetallic compound contacts a carrier channel located at the interface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.