Vertical GaN JFET with gate source electrodes on regrown gate

US8698164B2 · kind B2 · utility

Assignee

• Avogy, Inc. · US

Inventors

• Donald R. Disney · Cupertino, US
• Hui Nie · Cupertino, US
• Isik C. Kizilyalli · San Francisco, US
• Richard J. Brown · Los Gatos, US

Key dates

• Filing date: Dec 9, 2011
• Grant date: Apr 15, 2014
• Expiry date: Feb 16, 2032

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/111

Abstract

A semiconductor structure includes a GaN substrate with a first surface and a second surface. The GaN substrate is characterized by a first conductivity type and a first dopant concentration. A first electrode is electrically coupled to the second surface of the GaN substrate. The semiconductor structure further includes a first GaN epitaxial layer of the first conductivity type coupled to the first surface of the GaN substrate and a second GaN layer of a second conductivity type coupled to the first GaN epitaxial layer. The first GaN epitaxial layer comprises a channel region. The second GaN epitaxial layer comprises a gate region and an edge termination structure. A second electrode coupled to the gate region and a third electrode coupled to the channel region are both disposed within the edge termination structure.