Package substrate and semiconductor package including the same
US8698311B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 30, 2012 |
| Grant date | Apr 15, 2014 |
| Priority date | — |
| Expiry date | Aug 30, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A package substrate may include an insulating substrate, a dummy pad, a signal pad and a plug. The dummy pad may be formed on an upper surface of the insulating substrate. The signal pad may be formed on the upper surface of the insulating substrate. The signal pad may have an upper surface protruded from an upper surface of the dummy pad. The plug may be vertically formed in the insulating substrate. The plug may have an upper end exposed through the upper surface of the insulating substrate and connected with the signal pad and the dummy pad, and a lower end exposed through a lower surface of the insulating substrate. Thus, a signal bump may accurately make contact with the protruded upper surface of the signal pad.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.