Superfilled metal contact vias for semiconductor devices
US8698318B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 6, 2013 |
| Grant date | Apr 15, 2014 |
| Priority date | — |
| Expiry date | Feb 6, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In accordance with one aspect of the invention, a method is provided for fabricating a semiconductor element having a contact via. In such method, a hole can be formed in a dielectric layer to at least partially expose a region including at least one of semiconductor or conductive material. A seed layer can be deposited over a major surface of the dielectric layer and over a surface within the hole. In one embodiment, the seed layer can include a metal selected from the group consisting of iridium, osmium, palladium, platinum, rhodium, and ruthenium. A layer consisting essentially of cobalt can be electroplated over the seed layer within the hole to form a contact via in electrically conductive communication with the region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.