Memory element and memory device
US8699260B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 9, 2012 |
| Grant date | Apr 15, 2014 |
| Priority date | — |
| Expiry date | Jun 21, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8833
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
There are provided a memory element and a memory device with improved writing and erasing characteristics during operations at a low voltage and a low current. The memory element includes a first electrode, a memory layer, and a second electrode in this order. The memory layer includes a resistance change layer provided on the first electrode side, an ion source layer provided on the second electrode side, an intermediate layer provided between the resistance change layer and the ion source layer, and a barrier layer provided at least either between the ion source layer and the intermediate layer, or between the intermediate layer and the resistance change layer, and the barrier layer containing a transition metal or a nitride thereof.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.