Digital counter segmented into short and long access time memory
US8700874B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 24, 2010 |
| Grant date | Apr 15, 2014 |
| Priority date | — |
| Expiry date | Nov 15, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K21/16
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method performed in a memory controller for maintaining segmented counters split into primary and secondary memories, the primary memory faster. Events occur that require incrementing one of the segmented counters and the memory controller responds by incrementing a corresponding primary part in the primary memory. Each time a primary part is rolling over the memory controller determines that a secondary part should be updated. Also, the memory controller periodically determines that the secondary part of a segmented counter should be opportunistically updated. The opportunistic update is based on a probability function and a random number. The secondary part includes at least all of bits of the segmented counter not in the primary part and is stored in the secondary memory. Each time an update to the secondary part occurs, both the secondary part and primary part of the segmented counter must be updated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.