Design, layout, and manufacturing techniques for multivariant integrated circuits
US8701057B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 11, 2011 |
| Grant date | Apr 15, 2014 |
| Priority date | — |
| Expiry date | Sep 9, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit (IC) is designed that includes one variant having a plurality of a modular circuits communicatively coupled together and a second variant having a sub-set of the plurality of modular circuits. The modular circuits are then laid out on a wafer for fabricating each of the variants of the IC. The layout includes routing communicative couplings between the sub-set of the modular circuits of the second variant to the other modular circuits of the first variant in one or more metallization layers to be fabricated last. Fabricating the IC is then started, up to but not including the one or more metallization layers to be fabricated last. One or more of the plurality of variants of the IC is selected based upon a demand predicted during fabrication. Fabrication then continues with the last metallization layers of the IC according to the selected layout.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.