Methods, systems, and articles of manufactures for implementing electronic circuit designs with IR-drop awareness
US8701067B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 22, 2011 |
| Grant date | Apr 15, 2014 |
| Priority date | — |
| Expiry date | Jul 22, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/394
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed are a method, system, and computer program product for implementing electronic circuit designs with IR-drop awareness. Some embodiments perform schematic level simulation(s) to determine electrical characteristics, identifies physical parasitics of a layout component, determines the electrical or physical characteristics associated to IR-drop analysis on the component, and determines whether the component meets IR-drop related constraint(s) while implementing the physical design of the electronic circuit in some embodiments. Some embodiments further determine adjustment(s) to the component or related data where the IR-drop related constraints are not met and/or and present the adjustment(s) in the form of hints. Various data and information, such as currents in various forms or voltages, are passed between various schematic level tools and physical level tools.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.