Lithography process
US8703368B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 16, 2012 |
| Grant date | Apr 22, 2014 |
| Priority date | — |
| Expiry date | Jul 16, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG03F7/70633
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A process for use in lithography, such as photolithography for patterning a semiconductor wafer, is disclosed. The process includes receiving an incoming semiconductor wafer having various features and layers formed thereon. A unit-induced overlay (uniiOVL) correction is received and a deformation measurement is performed on the incoming semiconductor wafer in an overlay module. A deformation-induced overlay (defiOVL) correction is generated from the deformation measurement results by employing a predetermined algorithm on the deformation measurement results. The defiOVL and uniiOVL corrections are fed-forward to an exposure module and an exposure process is performed on the incoming semiconductor wafer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.