Wafer-level packaging mechanisms
US8703542B2 · kind B2 · utility
568Cited by
1References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 29, 2012 |
| Grant date | Apr 22, 2014 |
| Priority date | — |
| Expiry date | Jun 29, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18162
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The embodiments of mechanisms of wafer-level packaging (WLP) described above utilize a planarization stop layer to determine an end-point of the removal of excess molding compound prior to formation of redistribution lines (RDLs). Such mechanisms of WLP are used to implement fan-out and multi-chip packaging. The mechanisms are also usable to manufacture a package including chips (or dies) with different types of external connections. For example, a die with pre-formed bumps can be packaged with a die without pre-formed bumps.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.