Package carrier and manufacturing method thereof
US8704101B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 2, 2012 |
| Grant date | Apr 22, 2014 |
| Priority date | — |
| Expiry date | Oct 18, 2032 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49139
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a manufacturing method of a package carrier, a substrate having an upper surface, a lower surface, and an opening communicating the two surfaces is provided. An electronic device is disposed inside the opening. A first insulation layer and a superimposed first metal layer are laminated on the upper surface; a second insulation layer and a superimposed second metal layer are laminated on the lower surface. The opening is filled with the first and second insulation layers. First blind holes, second blind holes, and a heat-dissipation channel are formed. A third metal layer is formed on the first and second blind holes and an inner wall of the heat-dissipation channel. A heat-conducting device is disposed inside the heat-dissipation channel and fixed into the heat-dissipation channel via an insulation material. The first and second metal layers are patterned to form a first patterned metal layer and a second patterned metal layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.