Semiconductor test structures
US8704224B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 23, 2011 |
| Grant date | Apr 22, 2014 |
| Priority date | — |
| Expiry date | Jul 26, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A resistive test structure that includes a semiconductor substrate with an active region, a gate stack formed over the active region, a first electrical contact in communication with the active region on opposing sides of the gate stack, the first electrical contact providing an electrical short across a first dimension of the gate stack, and a second electrical contact in communication with the active region on the opposing sides of the gate stack, the second electrical contact providing an electrical short across the first dimension of the gate stack, the first and second electrical contacts spaced along a second dimension of the gate stack perpendicular to the first dimension.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.