Methods for forming etch stop layers, semiconductor devices having the same, and methods for fabricating semiconductor devices
US8704288B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 21, 2011 |
| Grant date | Apr 22, 2014 |
| Priority date | — |
| Expiry date | May 12, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/50
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A plurality of vertical channels of semiconductor material are formed to extend in a vertical direction through the plurality of insulation layers and the plurality of conductive patterns, a gate insulating layer between the conductive pattern and the vertical channels that insulates the conductive pattern from the vertical channels. Conductive contact regions of the at least two of the conductive patterns are in a stepped configuration. An etch stop layer is positioned on the conductive contact regions, wherein the etch stop layer has a first portion on a first one of the plurality of conductive patterns and has a second portion on a second one of the plurality of conductive patterns, wherein the first portion is of a thickness that is greater than a thickness of the second portion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.