Strained Ge-on-insulator structure and method for forming the same
US8704306B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 25, 2011 |
| Grant date | Apr 22, 2014 |
| Priority date | — |
| Expiry date | Sep 25, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/822
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A strained Ge-on-insulator structure is provided, comprising: a silicon substrate, in which an oxide insulating layer is formed on a surface of the silicon substrate; a Ge layer formed on the oxide insulating layer, in which a first passivation layer is formed between the Ge layer and the oxide insulating layer; a gate stack formed on the Ge layer; and a channel region formed below the gate stack, and a source and a drain formed on sides of the channel region, in which the source and the drain are a SixGe1-x:C source and a SixGe1-x:C drain respectively to produce a tensile strain in the channel region, in which x is within a range from 0 to 1 and a content of C is within a range from 0 to 7.5%. Further, a method for forming the strained Ge-on-insulator structure is also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.