Architecture for VBUS pulsing in UDSM processes
US8704550B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 29, 2007 |
| Grant date | Apr 22, 2014 |
| Priority date | — |
| Expiry date | Nov 29, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02J7/00
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Architecture for VBUS pulsing in an Ultra Deep Sub Micron (UDSM) process for ensuring USB-OTG (On The Go) session request protocol, the architecture being of the type wherein at least a charging circuit is deployed, uses a diode-means connected in a forward path of the charging circuit. The architecture might include a diode-divider including nodes and connected from VBUS in said charging circuit. One embodiment uses both charging and discharging circuits comprising transistors. The charging circuit transistor might comprise a PMOS transistor and the discharging circuit transistor might comprise a NMOS transistor. The architecture might include a three resistance string of a total resistance value approximating 100K Ohms connected between said VBUS and ground, wherein the discharging circuit transistor might comprise a drain extended NMOS transistor. The charging and discharging circuit transistors have VDS and VGD of about 3.6V, whereby high VGS transistors are not needed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.