Variable line size prefetcher for multiple memory requestors
US8706969B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 25, 2011 |
| Grant date | Apr 22, 2014 |
| Priority date | — |
| Expiry date | Feb 19, 2032 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A prefetch unit generates prefetch addresses in response to an initial received memory read request, an address associated with the initial received memory read request, a line length of the requestor of the initial received memory read request, and a request type width of the initial received memory read request. Prefetch operations are generated using the generated prefetch addresses, wherein each generated prefetch address is stored in a prefetch buffer slot that is selected by a prefetch FIFO (First In First Out) prefetch counter. Subsequent hits on the prefetcher result in returning prefetched data to the requestor in response to a subsequent memory read request received after the initial received memory read request.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.