Memory error detection
US8707110B1 · kind B1 · utility
13Cited by
129References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 6, 2013 |
| Grant date | Apr 22, 2014 |
| Priority date | — |
| Expiry date | Sep 6, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/09
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods are provided for detecting and correcting address errors in a memory system. In the memory system, a memory device generates an error-detection code based on an address transmitted via an address bus and transmits the error-detection code to a memory controller. The memory controller transmits an error indication to the memory device in response to the error-detection code. The error indication causes the memory device to remove the received address and prevent a memory operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.