Fault diagnosis based on design partitioning
US8707232B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 8, 2012 |
| Grant date | Apr 22, 2014 |
| Priority date | — |
| Expiry date | Jun 8, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2117/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Aspects of the invention relate to techniques for fault diagnosis based on circuit design partitioning. According to various implementations of the invention, a circuit design of a failing die is first partitioned into a plurality of sub-circuits. The sub-circuits may be formed based on fan-in cones of observation points. Shared gate ratios may be used as a metric for adding fan-in cones of observation points into a sub-circuit. Based on test patterns and the sub-circuits, sub-circuit test patterns are determined. Fault diagnosis is then performed on the sub-circuits. The sub-circuit fault diagnosis comprises extracting sub-circuit failure information from the failure information for the failing die. The sub-circuit fault diagnosis may employ fault-free values for boundary gates in the sub-circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.