Nanoparticles in a flash memory using chaperonin proteins
US8709892B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 22, 2006 |
| Grant date | Apr 29, 2014 |
| Priority date | — |
| Expiry date | May 25, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10K85/761
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A method for fabricating a flash memory device where the flash memory device includes a substantially uniform size and spatial distribution of nanoparticles on a tunnel oxide layer to form a floating gate. The flash memory device may be fabricated by defining active areas in a substrate and forming an oxide layer on the substrate. A self-assembled protein lattice may be formed on top of the oxide layer where the self-assembled protein lattice includes a plurality of molecular chaperones. The cavities of the chaperones may provide confined spaces where nanocrystals can be trapped thereby forming an ordered nanocrystal lattice. A substantially uniform distribution of nanocrystals may be formed on the oxide layer upon removal of the self-assembled protein lattice such as through high temperature annealing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.