3D structured memory devices and methods for manufacturing thereof
US8709894B2 · kind B2 · utility
27Cited by
2References
6Claims
0Family size
Assignee
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Key dates
| Filing date | Sep 16, 2011 |
| Grant date | Apr 29, 2014 |
| Priority date | — |
| Expiry date | Oct 14, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/324
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A 3D structured nonvolatile semiconductor memory devices and methods for manufacturing are disclosed. One such device includes an n+ region at a source/drain region; a p+ region at the source/drain region; and a diffusion barrier material between the n+ region and the p+ region. The n+ region is substantially isolated from the p+ region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.