Method for testing multi-chip stacked packages
US8710859B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 23, 2011 |
| Grant date | Apr 29, 2014 |
| Priority date | — |
| Expiry date | Jun 13, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318513
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Disclosed is a method for testing multi-chip stacked packages. Initially, one or more substrate-less chip cubes are provided, each consisting of a plurality of chips such as chips stacked together having vertically connected with TSV's where there is a stacked gap between two adjacent chips. Next, the substrate-less chip cubes are adhered onto an adhesive tape where the adhesive tape is attached inside an opening of a tape carrier. Then, a filling encapsulant is formed on the adhesive tape to completely fill the chip stacked gaps. Next, the tape carrier is fixed on a wafer testing carrier in a manner to allow the substrate-less chip cubes to be loaded into a wafer tester without releasing from the adhesive tape. Accordingly, the probers of the wafer tester can be utilized to probe testing electrodes of the substrate-less chip cubes so that it is easy to integrate this testing method in TSV fabrication processes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.