Circuit arrangement having a load transistor and a voltage limiting circuit and method for driving a load transistor
US8710894B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 16, 2012 |
| Grant date | Apr 29, 2014 |
| Priority date | — |
| Expiry date | Mar 16, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/611
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a circuit arrangement having the following features: a load transistor having a control connection and a first and second load connection; a drive connection coupled to the control connection of the load transistor and serving for the application of a drive signal; a voltage limiting circuit connected between one of the load connections and the drive connection of the transistor; and a deactivation circuit connected to the voltage limiting circuit and serving for the deactivation of the voltage limiting circuit in a manner dependent on a deactivation signal, which is dependent on a load current through the load transistor and/or on a drive voltage of the load transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.