Fine grain voltage scaling of back biasing
US8710906B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 12, 2013 |
| Grant date | Apr 29, 2014 |
| Priority date | — |
| Expiry date | Feb 12, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit including a substrate, multiple devices, and voltage control devices. The devices may include high threshold, low threshold, and standard threshold voltage devices. The devices and the voltage control devices are distributed across and coupled to the same substrate. Each voltage control device is configured to apply a back bias voltage at one of multiple discrete offset voltage levels. At least one voltage control device applies a first offset voltage level for back biasing high threshold voltage devices and at least one voltage control device applies a second offset voltage level for back biasing low threshold voltage devices. The selection of back biasing is based on relative population density of the different types of devices and varies across the substrate. Fine grain reverse back biasing reduces leakage current while reducing any performance decrease. Fine grain forward back biasing improves performance while reducing any leakage current increase.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.